Chapter 01: Your First HDL Module

The Fundamental Truth

Every piece of hardware does one thing: it takes electrical signals IN and produces electrical signals OUT. That's it. An FPGA lets you define what happens between IN and OUT.

The Simplest Module: AND Gate

Let's build an AND gate. It has 2 inputs and 1 output. Output is HIGH only when BOTH inputs are HIGH.

Truth Table

A  B  |  Y
--------+----
0  0  |  0
0  1  |  0
1  0  |  0
1  1  |  1

The Verilog Code

Create a file called and_gate.v in your project:

// This is your first hardware module
// It describes a 2-input AND gate

module and_gate (
    input  a,      // First input wire
    input  b,      // Second input wire
    output y       // Output wire
);

    // This single line describes the AND operation
    // 'assign' means: "wire y is ALWAYS connected to (a AND b)"
    assign y = a & b;

endmodule

What Actually Happens

1. The FPGA synthesis tool reads this file - It understands you want an AND gate
2. It allocates hardware resources - Uses 2 input pins, 1 output pin, and 1 LUT (Look-Up Table)
3. It programs the LUT - Configures it to output the AND truth table
4. It connects physical wires - Routes signals from pins through the LUT

Connecting to Real Pins

Create and_gate.cst to map your module to physical pins on the Tang Primer 20K:

//===========================================
// Pin Constraints for AND Gate
// Tang Primer 20K (GW2A-18C)
//===========================================

// Button S1 → Input A
IO_LOC  "a" T3;
IO_PORT "a" PULL_MODE=UP IO_TYPE=LVCMOS33;

// LED 0 → Input B (we'll use LED as input for testing)
IO_LOC  "b" L16;
IO_PORT "b" IO_TYPE=LVCMOS33;

// LED 1 → Output Y
IO_LOC  "y" L14;
IO_PORT "y" DRIVE=8 IO_TYPE=LVCMOS33;

Build and Test

1. Create new project in Gowin IDE
2. Add and_gate.v as source file
3. Add and_gate.cst as constraint file
4. Set device to GW2A-LV18PG256C8/I7
5. Click Synthesize → Place & Route → Program Device

Key Concepts You Just Learned

• module - Defines a hardware block with inputs and outputs
• input/output - Declares physical connections (wires)
• assign - Creates permanent connections between signals
• & - Bitwise AND operator (creates AND gate hardware)
• IO_LOC - Maps signal names to physical FPGA pins
• IO_PORT - Configures electrical properties of pins